Makefile target and extra parameters to $(MAKE)

[Riccardo Mottola]

Hi,

I think I understand why I have issues with gnustep-back extra CPPFLAGS, 
BUILD_ARGS and others.
I wrote my own build target this way:

build-sourcegs:
         $(BUILD_ENV) && . 
$(BUILD_PREFIX)/GNUstep/System/Library/Makefiles/GNUstep.sh && cd 
$(WORKSRC) && $(MAKE)
         @$(MAKECOOKIE)

and "make" is just the Make binary, isn't it? not something that gets 
expanded with all parameters.

Is there a variable equivalent to $(BUILD_ENV) to pass additionally and 
have the needed parameters? E.g. I can do

  $(MAKE) $(BUILD_ARGS)

But that is just for BUILD_ARGS, what else could I be missing?

I tried:

$(MAKE) $(BUILD_ARGS) CPPFLAGS=$(EXTRA_CPPFLAGS)

and this fixes my specific issue, but it is of course "naive" since it 
doesn't escape anything and also could miss many other variables, but I 
hope I was able to express what I am seeking for, am I?
Maybe there is a ready variable to use or a set of known parameters to 
copy from e.g. a mgar file, the standard one invoked if by build.

Thanks for your suggestions.

Riccardo